Dynamic threshold voltage control improves the ON/OFF current ratio for a FET such that the threshold voltage can be low when the FET is on to provide a high current, and the threshold voltage can be high when the device is off to prevent leakage. Such dynamic threshold voltage control has been previously achieved through the use of body-bias. However, the various body-bias techniques incur additional costs such as for an additional power supply and a body bias control circuit, for a body contact for each FET, for additional wiring, a circuit for threshold voltage control, and three-dimensional (3-D) structures, or for introduction of ferroelectric materials to the CMOS platform. Recent attempts related to charge-trapping have further improved the ON/OFF current ratio. The additional improvements have led to an ON/OFF current ratio such that in an off state, a high threshold voltage gives a low current off and in an on state, a low threshold voltage give a high current on. In the case of FETs used in static random-access memory (SRAM), minimum voltages may be increased by 170 millivolts (mV) and active power (e.g., Cload (capacitance load)*Vdd2 (e.g., low supply voltage)) and standby power (e.g., Ioff (current off)*Vdd/frequency) may be reduced. However, such improvements in the ON/OFF current ratio have resulted in charging times of microseconds, which lead to a low switching speed. Thus, resulting devices are only useful for power switches and field-programmable gate array switches.
A need therefore exists for methodology enabling formation of high performance FETs with short charging times and improved ON/OFF current ratios, and the resulting devices.